The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of reducing the effect of gate induced drain leakage (GIDL), and a method for manufacturing the same.
As high integration of a semiconductor device has continued to proceed, a channel length of a transistor has been shortened and an ion implantation concentration of source and drain areas has been increased. As a result of these changes, a short channel effect has became a serious problem in which a threshold voltage (Vt) is lowered as charge sharing between the source area and the drain area is increased. In addition, controllability of a gate is reduced. Also, a refresh property deteriorates due to an increase in junction leakage current that results from an increase in an electric field in the source area and the drain area. Therefore, conventional semiconductor devices with a planar channel offer limited capability for overcoming problems that result from high integration.
For this reason, research has been actively performed to fabricate a semiconductor device with a recess channel, which is capable of improving an effective channel length.
Hereinafter, a method for manufacturing a semiconductor device having a conventional recess channel will be briefly described.
After an isolation layer is formed in an isolation region of a semiconductor substrate having an active region including a gate forming area and the isolation region, a screen oxide layer is formed over an entire surface of the semiconductor substrate that is formed with the isolation layer. Ion implantation is performed to adjust a threshold voltage. An ion implantation of the source/drain is sequentially performed on the semiconductor substrate formed with the screen oxide layer. The screen oxide layer is then removed.
After a mask pattern that is used for exposing the gate forming area of the active region is formed over the ion implanted semiconductor substrate, the portion of the semiconductor substrate exposed by the mask pattern is etched to form a recess in the gate forming area of the active region. The mask pattern is then removed.
After a gate insulation layer is formed over the semiconductor substrate including the recess, a gate conductive layer is formed over the gate insulation layer to fill in the recess. The gate insulation layer is formed as an oxide layer and the gate conductive layer is formed as a laminated layer of a polysilicon layer and a tungsten layer. A hard mask layer made of a nitride layer is then formed over the gate conductive layer.
By patterning the hard mask layer, the gate conductive layer, and the gate insulation layer, a transistor having a recess channel is formed in the gate forming area that includes the recess.
A series of known follow up processes are sequentially performed, thereby completing formation of a semiconductor device having the recess channel.
Meanwhile, as aforementioned, as a cell size has been scaled down with high integration of the semiconductor device, a channel doping concentration has been excessively increased to maintain the threshold voltage at the same level. As a result, the refresh property deteriorates.
For this reason, in order to prevent deterioration of the refresh property, a method has been proposed to adjust the threshold voltage (Vt) by applying a P+ polysilicon layer instead of an N+ polysilicon layer.
When applying the P+ polysilicon layer instead of the N+ polysilicon layer, it is possible to significantly decrease the channel doping concentration. The threshold voltage can be ensured even with a low channel dose through a difference in band gap voltage of the semiconductor substrate made of silicon. Also, the refresh property can be improved.
However, in the case of applying the P+ polysilicon layer to the recess channel structure, a band gap is seriously bent due to a Fermi level difference, e.g., approximately 1.1V, between the source/drain area and the gate. As a result, a GIDL phenomenon results at an upper end portion of a side wall of the recess adjacent to the source area, which in turn increases the leakage current and deteriorates the refresh property.
In a GIDL phenomenon, current leaks in the form of an electric field and is concentrated into both edge portions where the gate and the semiconductor substrate contact each other. GIDL is a problem which should be addressed to improve device properties and reliability. Also, GIDL is a major factor in reducing a refresh time of the device.